OpenPPG — E-Plane Throttle Quadrant Revision Report

Executive summary

This is a targeted reliability and manufacturability revision of the board previously prototyped at c457569. It separates the MCP25625 CAN controller from the shared SPI bus, cleans the copper routing standard, and tightens local power and clock placement—while preserving the board outline, connector plan, component count, and low-cost two-layer construction.

3new dedicated CAN SPI nets

5critical parts repositioned

0 / 0PCB DRC errors / unrouted pads

Same57 footprints · 94.22 × 40.10 mm outline

What changed — and why

Electrical comparisons come from the KiCad schematic and PCB at the two exact commits; dimensions and route counts were read directly from the board database.

Dedicated CAN-controller SPI

MCP25625 pins 14–16 moved from shared SCK/MOSI/MISO to CAN_SCK/CAN_MOSI/CAN_MISO, using ESP32-S3 GPIO 5, 21 and 41. The display and MA730 remain on the original bus.removes CAN traffic from the multi-device SPI path, reducing bus-contention risk and simplifying firmware timing and recovery.

Disciplined signal routing

New routing was normalized to 45° geometry and a short metric width palette. Legacy 0.254 / 0.381 / 0.508 / 0.635 mm widths were removed; CAN SPI is fixed at 0.15 mm, with 0.20 / 0.25 mm used for general signals and wider copper reserved for power.makes each route’s electrical intent obvious and prevents unexplained width changes inside ordinary signal runs.

Regulator decoupling placement

C5, the +12 V input bulk capacitor, moved 13.77 mm and flipped to the bottom side beside U1. C2, the +5 V output bulk capacitor, moved 8.77 mm to the regulator output area.shortens the input/output current loops around the R-78E regulator and improves transient and conducted-noise behavior.

CAN clock and local bypass cleanup

Y1 moved 0.50 mm toward U5; C9 moved 0.50 mm and C10 moved 1.00 mm toward their loads. Both MCP25625 oscillator routes were made consistently 0.25 mm.reduces critical loop area and keeps the 16 MHz clock and local supply return paths compact and predictable.

Fabrication rules with margin

Global minimum track width increased from 0.10 to 0.15 mm. Minimum via changed from 0.35 / 0.20 mm to 0.60 / 0.30 mm, while copper-to-edge remains 0.508 mm. A scoped 0.10 mm clearance applies only to the three dedicated CAN SPI nets.keeps the dense route on a standard 1 oz, two-layer process while using more robust drills and annular copper everywhere else.

Auditable design baseline

The repository now carries a formal review package: BOM, Gerbers, drill and placement files, PCB/schematic PDFs, STEP model, DRC/ERC reports, SKiDL source/netlists, and the design-review record.gives future revisions a reproducible manufacturing reference instead of relying on an editor state or a single production zip.

Scope boundary

This spin does not change the footprint set, connector map, mounting pattern, board envelope, or layer count. It is a focused controller-interface and layout-quality revision—not a product-certification or full protection-architecture redesign.

Physical revision comparison

Render note: all connector bodies are displayed for mechanical clarity. J1, J2, J6 and J8 remain marked DNP in the current KiCad source; only the render-only copy was unhidden.

Current top-side 3D render at commit 458fdbf — Prototype shown on the left of the dividerCurrent revision shown on the right

Prototype top-side 3D render at commit c457569 — Prototype shown on the left of the dividerCurrent revision shown on the right

Current bottom-side 3D render at commit 458fdbf — Prototype shown on the left of the dividerCurrent revision shown on the right

Prototype bottom-side 3D render at commit c457569 — Prototype shown on the left of the dividerCurrent revision shown on the right

Validation & manufacturing readiness

Connectivity complete0 unconnected pads; schematic and PCB both carry the three dedicated CAN SPI nets.

PCB DRC: 0 errorsFour remaining messages are pre-existing silkscreen-overlap warnings, not copper or connectivity failures.

JLCPCB-compatible geometry0.15 mm minimum track, 0.10 mm scoped clearance, 0.30 mm minimum drill, 0.508 mm edge clearance.

Cost target preservedSame 2-layer, 1 oz, 1.6 mm construction and unchanged physical envelope.

E-Plane Throttle Quadrant — Controller Board Revision Report